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| 1 | Looking into the future of Nanoelectronics in the Diversification Efficient Era显示文摘The linear scaling of CMOS has encountered, since its beginning, many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10 nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described. | Simon DELEONIBUS | 2016 | Science China(Information Sciences)2016，59，6： | 4 |
| 2 | Ultra-thin films and multigate devices architectures for future CMOS scaling显示文摘The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform. | DELEONIBUS Simon | 2011 | Science China(Information Sciences)2011，54，5： | 3 |
| 3 | Physical and technological limitations of Nano- CMOS devices to the end of the roadmap and beyond 显示文摘 | DELEONIBUS S | 2006 | Eu- ropean Physical Journal Applied Physics2006，36，3： | 1 |
| 4 | Col apse of MOSFET drain cur ent after soft breakdown显示文摘 | Cester A Paccagnel a A GhidiniG Deleonibus S Guegan G | | 0，，： | 1 |
| 5 | Editor's note显示文摘The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10–20 d B lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter(ADC) chips with more than 24 bits in the market. In this paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus facilitating higher resolution and larger dynamic range seismic data acquisition. Experimental results show that, within the 0.1–40 Hz frequency range, the circuit board's dynamic range reaches 158.2 d B, its resolution reaches 25.99 bits, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even completely resolve the amplitude-limitation problem that so commonly occurs with broadband observation instruments during strong earthquakes. | Ru HUANG Hiroshi IWAI Cor CLAEYS Simon DELEONIBUS Runsheng WANG | 2016 | Science China(Information Sciences)2016，59，6： | 1 |
| 6 | Physical and technological limitations of nano CMOS devices to the end of the road map and beyond 显示文摘 | DELEONIBUS S | 2006 | EPJ Applied Physics2006，36，3： | 1 |
| 7 | Physical and technological limitations ofnano CMOS devices to the end of the roadmap and beyond显示文摘 | DELEONIBUS S | 2006 | European Physical Journal Applied Physics2006，36，03： | 1 |
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