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您的检索式：作者名="Rajeevan Chandel"
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| 1 | Delay analysis of a single voltage scaled repeater driven long interconnect显示文摘 | Rajeevan Chandel Sarkar S Agarwal R P | 2005 | Microelectronics International2005，22，3： | 1 |
| 2 | Comparative study of ant colony and genetic algorithm for VLSI circuit partitioning 显示文摘 | Gill Sandeep Singh Chandel Rajeevan Chandel Ashwani | 2009 | Inter''national Journal of Intelligent Systems and Technologies2009，4，2： | 1 |
| 3 | Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS显示文摘With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability. | Neha Sharma Rajeevan Chandel | 2021 | International Journal of Modeling, Simulation, and Scientific Computing2021，12，4： | 0 |
| 4 | Efficient Clustering and Simulated Annealing Approach for Circuit Partitioning显示文摘Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized.The proposed method begins with an innovative clustering technique to obtain a good initial solution.Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature. | SANDEEP Singh Gill RAJEEVAN Chandel ASHWANI Kumar Chandel | 2011 | Journal of Shanghai Jiaotong university(Science)2011，16，6： | 0 |
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